1. Field of Invention
The present invention relates to the measurement of capacitances, and more specifically to measurement of the coupling capacitance between interconnect lines of an integrated circuit (IC) structure.
2. Description of Related Art
As transistor scaling continues, gate delay is no longer the major limit of circuit speed and instead interconnect delay dominates the circuit performance. In addition, as interconnection becomes multi-layers, more complex and more close, the crosstalk coupling effect between wires becomes a source of noise in deep sub-micron analog and digital circuits, which can result in chip functional failures. Therefore, to extract accurate interconnect parameters for circuit simulation or for circuit failure analysis is needed and important.
In order to evaluate the coupling effect between interconnect lines, it's necessary to ascertain the coupling capacitances between lines. The coupling capacitance includes both intra-layer capacitance, which occurs in a same layer, and inter-layer capacitance, which occurs in different layers. Some reasons to show the necessity for measurement accuracy of lateral intra-layer coupling capacitance parameters are as follows. First, increasing metal aspect ratio (thickness/width) can improve RC delay, but the performance benefit will eventually saturate when the lateral intra-layer coupling capacitance becomes the dominant contributor to the wire total capacitance, as reported by M. Bohr, “Interconnect scaling—the real limiter to high performance ULSI,” IEEE Tech. Digest IEDM, 1995, pp. 241-244. Second, in order not to increase interconnect resistance significantly, metal thickness is not scaled with the metal pitch and usually is kept to be the same. As a result, the lateral intra-layer coupling capacitance will be the dominant portion of total wire capacitance in advanced processes.
There are two types of test structures that are normally used to measure interconnect coupling capacitances, the off-chip or passive test structures and the on-chip or active test structures. The passive test structures require very large geometries to increase capacitance values and the capacitance is measured directly using an impedance meter. Unlike the off-chip direct method, the on-chip method uses active devices to apply currents to charge or discharge capacitances of the interconnect lines. In this method, capacitance is a derived quantity, obtained by measuring the capacitive currents, and hence this method is an indirect method. One indirect method, called as Charge Based Capacitance Measurement (CBCM), was proposed by Bernard Laquai et al., “An new method and test structure for easy determination of femto-farad on-chip capacitance in a MOS process,” Proc. IEEE, vol. 5, 1992, pp. 62-66. The approach uses the average current supplied to the inverter and the given clock frequency to derive the loading capacitance, which can make a measurement with femto-farad resolution. J. Chen et al. disclosed an improved test method with 0.01fF resolution in “An on-chip attofarad interconnect charge-based capacitance measurement (CBCM) technique,” Proc. of IEDM, 1996, pp. 69-72 and “An on-chip, interconnect capacitance characterization method with sub-femto-farad resolution,” IEEE Transactions on Semiconductor Manufacturing, Vol. 11, 1998.
In the CBCM technique, a pair of inverters with two individual test structures 112, a target test structure and a dummy/reference test structure, are used to deduce the wanted capacitance as shown in FIG. 1. The substrate in an IC chip on which the integrated circuits and test structures are formed is normally treated as a ground plane (grounded). The two test structures 112 are coupled to the output terminals Vout1 and Vout2 of the two inverters respectively. The left-hand side inverter in FIG. 1 is comprised of a pair of transistors, a first P type Metal-Oxide-Semiconductor (PMOS) transistor 102 and a first N type Metal-Oxide-Semiconductor (NMOS) transistor 104. The right-hand side inverter in FIG. 1 is comprised of a pair of transistors, a second PMOS transistor 114 and a second NMOS transistor 116. Clock voltage signals V1 and V2 are two non-overlap signals, whose waveforms are shown in FIG. 2, to avoid a direct current path (short path) from power supply terminal 106 (with a voltage Vdd) to ground 110 at transients during signal switching. Two DC current meters 108 denoted by A1 and A2 are used to monitor the currents flowing through the inverters in FIG. 1, respectively. Here, only average currents need to be measured.
According to J. Chen's method, a target test structure for intra-layer capacitance extraction is illustrated in FIG. 3. It comprises a comb line 300 surrounded by a meander line 302. The meander line is connected to ground 304 and the comb line 300 is connected to the output terminal Vout1 of the left-hand side inverter in FIG. 1. The comb line 300 is laterally separated by a specific distance of s from the meander line 302. The total coupling capacitance includes the area, fringe, and line-to-line coupling components. To eliminate undesired components, a dummy test structure is designed as shown in FIG. 4. A comb line 400 is connected to the output terminal Vout2 of the right-hand side inverter in FIG. 1, and a short meander line 402 is connected to ground 404. The line-to-line coupling component for part of the comb line 300 of FIG. 3 with length L is to be extracted. The dummy test structure is intended to emulate the capacitance of the comb line 300 with respect to ground of FIG. 3 except the line-to-line coupling component between the comb line 300 and each of its neighboring parts of the meander line 302.
FIG. 5 and FIG. 6 are the cross-sectional views of FIG. 3 and FIG. 4, respectively. The connection of the meander line 302 to ground 304 is also shown in FIG. 5. FIG. 6 illustrates the cross section of only part of the comb line 400 without laterally neighboring parts of the meander line 402. The substrate of the IC chip is connected to ground 500. The average current I flowing through an inverter can be described as Eq. (1) where Vdd is the power supply voltage, f is the frequency of the clock signals V1 and V2, and the total loading capacitance of the output terminal of the inverter is Ctot.I=Ctot*Vdd*f  (1) According to FIG. 5 and FIG. 6, their total capacitances Ctot1, Ctot2 are composed as follows, respectively:Ctot1=2Cc+2Cf1+Ca1+Cstray1  (2) and Ctot2=2Cf2+Ca2+Cstray2  (3) In Eq. (2) for the target test structure, Cc denotes the target line-to-line coupling capacitance, Cf1 denotes the fringe capacitance between the lateral edge of the comb line 300 and the ground plane (substrate), Ca1 is the area capacitance between the bottom of the comb line 300 and the ground plane, and Cstray1 is the stray capacitance of the left-hand side inverter itself. Cf2, Ca2, and Cstray2 are the counterpart components for the dummy test structure.
If mismatching effect of the two inverters in FIG. 1 and interconnection is ignored, Cstray1 is equal to Cstray2 and Ca1 is equal to Ca2. The difference between the charging current I1 of the left-hand side inverter and the charging current I2 of the right-hand side inverter is given asI1−I2=(Ctot1−Ctot2)*Vdd*f=[2Cc+2(Cf1−Cf2)]*Vdd*f  (4) Generally, the fringe component is not negligible compared to the line-to-line coupling component. Moreover, due to different charge distributions between both of the comb lines 300, 400 with and without neighboring ground wires on the same layer and the substrate, Cf1 is smaller than Cf2 and the total coupling capacitance to substrate of a comb line without neighboring ground wires is much larger than that of the same comb line with neighboring ground wires. Because of the big difference between Cf1 and Cf2 introduced into Eq. (4), the extracted intra-layer coupling capacitance when the comb line 300 and the meander line 302 are in the same layer is inaccurate and underestimated. From a 2-D simulation on a 0.6 um technology, the metal-1 coupling capacitance to substrate of a comb line without neighboring wires is 2.6 times that with neighboring wires (Ca1+2Cf1=0.0395 fF/um, Ca2+2Cf2=0.1029 fF/um, width/space=0.6 um/0.6 um, dielectric thickness=7000 Angstrom, Cc is just only 0.092 fF/um). For the above reason, these two test structures are only suitable for inter-layer coupling capacitance extraction when the meander line is not in the same layer as the comb line, where the charge distributions are approximately the same.
Besides, the error induced by the mismatch between the two inverters is another important issue of CBCM method. If mismatch can't be ignored, the difference of the two total capacitances Ctot1, Ctot2 caused by the line-to-line coupling component will be larger, so the error will be larger. Arora et al proposed a new structure in U.S. Pat. No. 5,999,010, Dec. 7, 1999, which also adopted CBCM technique. However, this method requires three measurement steps and needs more pads to implement the test structure, thus it's not suitable for an on-wafer measurement.
For the forgoing reasons, there is a need for a method and measuring device for measuring the line-to-line coupling capacitance between interconnect lines in an IC chip.